On-Die Power Rail Measurements: Setup and Best Practices
Accurate on-die power rail measurements depend on proper sense-line design, differential probing, and careful test setup at the package level.
Characterizing PDN noise—whether from self-aggression, board coupling, or mutual aggressors—is essential to maintaining millivolt-level power integrity margins.
Power integrity concerns maintaining the quality of power from generation to consumption in an embedded system. “Good” power integrity could be defined as having noise levels that are within tolerance. This short series will focus on characterizing noise on your power delivery network (PDN), with the goal of knowing where you must adjust your design to meet those tolerances.
Why do we care about voltage rail noise? As electronic designs strive for ever lower power consumption, power rails already carry very low voltages, often 1 V or less. Components like RF receivers, ADCs and DACs can be affected by noise of less than 1% of the rail value (Figure 1). This means noise tolerances can be as tight as single-digit millivolts, which is why power integrity takes up considerable validation time in labs.

Figure 2 shows a common topology for a modern embedded system, which we’ll use to illustrate power integrity concepts. A board-level PDN consists primarily of:

Power integrity is most commonly addressed at the board level, but there are applications where it is desirable to look at the power integrity of the on-die distribution network inside an integrated device. (At the end of this post are links to previous posts discussing on-die power rail measurements.) Although these are usually considered separate realms, as we’ll show, there are cases where on-die effects can cause board noise, and vice versa.
First, let’s categorize the types of noise we expect to encounter in a PDN. Whether discussing on-board PDN or on-die PDN, noise can be placed into three broad categories:
Each type of noise requires distinct measuring techniques.
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